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1 8, 16 meg x 72 pc133/pc100 registered sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm28_3.p65 ? rev. 4/00 ?1999, micron technology, inc. 8, 16 meg x 72 registered sdram dimms advance note : symbols in parentheses are not used on these modules but may be used for other modules in this product family. they are for reference only. pin symbol pin symbol pin symbol pin symbol 1v ss 43 v ss 85 v ss 127 v ss 2 dq0 44 dnu 86 dq32 128 cke0 3 dq1 45 s2# 87 dq33 129 rfu (s3#) 4 dq2 46 dqmb2 88 dq34 130 dqmb6 5 dq3 47 dqmb3 89 dq35 131 dqmb7 6v dd 48 dnu 90 v dd 132 rfu (a13) 7 dq4 49 v dd 91 dq36 133 v dd 8 dq5 50 nc 92 dq37 134 nc 9 dq6 51 nc 93 dq38 135 nc 10 dq7 52 cb2 94 dq39 136 cb6 11 dq8 53 cb3 95 dq40 137 cb7 12 v ss 54 v ss 96 v ss 138 v ss 13 dq9 55 dq16 97 dq41 139 dq48 14 dq10 56 dq17 98 dq42 140 dq49 15 dq11 57 dq18 99 dq43 141 dq50 16 dq12 58 dq19 100 dq44 142 dq51 17 dq13 59 v dd 101 dq45 143 v dd 18 v dd 60 dq20 102 v dd 144 dq52 19 dq14 61 nc 103 dq46 145 nc 20 dq15 62 nc 104 dq47 146 nc 21 cb0 63 rfu (cke1) 105 cb4 147 rege 22 cb1 64 v ss 106 cb5 148 v ss 23 v ss 65 dq21 107 v ss 149 dq53 24 nc 66 dq22 108 nc 150 dq54 25 nc 67 dq23 109 nc 151 dq55 26 v dd 68 v ss 110 v dd 152 v ss 27 we# 69 dq24 111 cas# 153 dq56 28 dqmb0 70 dq25 112 dqmb4 154 dq57 29 dqmb1 71 dq26 113 dqmb5 155 dq58 30 s0# 72 dq27 114 rfu (s1#) 156 dq59 31 dnu 73 v dd 115 ras# 157 v dd 32 v ss 74 dq28 116 v ss 158 dq60 33 a0 75 dq29 117 a1 159 dq61 34 a2 76 dq30 118 a3 160 dq62 35 a4 77 dq31 119 a5 161 dq63 36 a6 78 v ss 120 a7 162 v ss 37 a8 79 ck2 121 a9 163 ck3 38 a10 80 nc 122 ba0 164 nc 39 ba1 81 wp 123 a11 165 sa0 40 v dd 82 sda 124 v dd 166 sa1 41 v dd 83 scl 125 ck1 167 sa2 42 ck0 84 v dd 126 rfu (a12) 168 v dd pin assignment (front view) synchronous dram module mt9lsdt872, mt9lsdt1672 for the latest data sheet, please refer to the micron web site: www.micronsemi.com/datasheets/datasheet.html 168-pin dimm features ? jedec-standard 168-pin, dual in-line memory module (dimm) pc133- and pc100-compliant registered inputs with one-clock delay phase-lock loop (pll) clock driver to reduce loading utilizes 133 mhz and 125 mhz sdram compo- nents ecc-optimized pinout 64mb (8 meg x 72) and 128mb (16 meg x 72) single +3.3v 0.3v power supply fully synchronous; all signals registered on positive edge of pll clock internal pipelined operation; column address can be changed every clock cycle internal sdram banks for hiding row access/ precharge programmable burst lengths: 1, 2, 4, 8, or full page auto precharge and auto refresh modes self refresh mode 64ms, 4,096-cycle refresh lvttl-compatible inputs and outputs serial presence-detect (spd) options marking package 168-pin dimm (gold) g frequency/cas latency* 133 mhz/cl = 2 -13e (7.5ns, 133 mhz sdrams) 133 mhz/cl = 3 -133 (7.5ns, 133 mhz sdrams) 100 mhz/cl = 2 -10e (8ns, 125 mhz sdram) *device latency only; extra clock cycle required due to input register. key sdram component timing parameters module speed cas access setup hold marking grade latency time time time -13e -7e 2 5.4ns 1.5ns 0.8ns -133 -75 3 5.4ns 1.5ns 0.8ns -10e -8e 2 6ns 2ns 1ns
2 8, 16 meg x 72 pc133/pc100 registered sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm28_3.p65 ? rev. 4/00 ?1999, micron technology, inc. 8, 16 meg x 72 registered sdram dimms advance general description the mt9lsdt872 and mt9lsdt1672 are high-speed cmos, dynamic random-access, 64mb and 128mb memories organized in a x72 configuration. these mod- ules use internally configured quad-bank sdrams with a synchronous interface (all signals are registered on the positive edge of clock signals ck0). read and write accesses to the sdram modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registra- tion of an active command, which is then followed by a read or write command. the address bits regis- tered coincident with the active command are used to select the bank and row to be accessed (ba0, ba1 select the bank, a0-a11 select the row). the address bits registered coincident with the read or write com- mand are used to select the starting column location for the burst access. these modules provide for programmable read or write burst lengths of 1, 2, 4, or 8 locations, or full page, with a burst terminate option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst se- quence. these modules use an internal pipelined architecture to achieve high-speed operation. this architecture is compatible with the 2 n rule of prefetch architectures, but it also allows the column address to be changed on every part numbers part number configuration system bus speed mt9lsdt872g-13e__ 8 meg x 72 133 mhz MT9LSDT872G-133__ 8 meg x 72 133 mhz mt9lsdt872g-10e__ 8 meg x 72 100 mhz mt9lsdt1672g-13e__ 16 meg x 72 133 mhz mt9lsdt1672g-133__ 16 meg x 72 133 mhz mt9lsdt1672g-10e__ 16 meg x 72 100 mhz note : all part numbers end with a two-place code (not shown), designating component and pcb revisions. consult factory for current revision codes. example: mt9lsdt1672g-133 b1 clock cycle to achieve a high-speed, fully random access. precharging one bank while accessing one of the other three banks will hide the precharge cycles and pro- vide seamless, high-speed, random-access operation. these modules are designed to operate in 3.3v, low- power memory systems. an auto refresh mode is pro- vided, along with a power-saving, power-down mode. all inputs and outputs are lvttl-compatible. sdram modules offer substantial advances in dram operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. for more information regarding sdram opera- tion, refer to the 64mb and 128mb sdram data sheets. pll and register operation these modules can be operated in either registered mode (rege pin high), where the control/address input signals are latched in the register on one rising clock edge and sent to the sdram devices on the following rising clock edge (data access is delayed by one clock), or in buffered mode (rege pin low) where the input signals pass through the register/buffer to the sdram devices on the same clock. a phase-lock loop (pll) on the modules is used to redrive the clock signals to the sdram devices to minimize system clock loading (ck0 is connected to the pll, and ck1, ck2 and ck3 are terminated). serial presence-detect operation these modules incorporate serial presence-detect (spd). the spd function is implemented using a 2,048- bit eeprom. this nonvolatile storage device contains 256 bytes. the first 128 bytes can be programmed by micron to identify the module type and various sdram organizations and timing parameters. the remaining 128 bytes of storage are available for use by the customer. system read/write operations between the master (system logic) and the slave eeprom device (dimm) occur via a standard iic bus using the dimm?s scl (clock) and sda (data) signals, together with sa(2:0), which provide eight unique dimm/eeprom addresses.
3 8, 16 meg x 72 pc133/pc100 registered sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm28_3.p65 ? rev. 4/00 ?1999, micron technology, inc. 8, 16 meg x 72 registered sdram dimms advance spd clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions (fig- ures 1 and 2). spd start condition all commands are preceded by the start condition, which is a high-to-low transition of sda when scl is high. the spd device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. spd stop condition all communications are terminated by a stop con- dition, which is a low-to-high transition of sda when scl is high. the stop condition is also used to place the spd device into standby power mode. spd acknowledge acknowledge is a software convention used to indicate successful data transfers. the transmitting device, either master or slave, will release the bus after transmitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data (figure 3). the spd device will always respond with an ac- knowledge after recognition of a start condition and its slave address. if both the device and a write operation have been selected, the spd device will re- spond with an acknowledge after the receipt of each subsequent eight-bit word. in the read mode the spd device will transmit eight bits of data, release the sda line and monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. if an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. scl sda data stable data stable data change figure 1 data validity scl sda start bit stop bit figure 2 definition of start and stop scl from master data output from transmitter data output from receiver 9 8 acknowledge figure 3 acknowledge response from receiver
4 8, 16 meg x 72 pc133/pc100 registered sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm28_3.p65 ? rev. 4/00 ?1999, micron technology, inc. 8, 16 meg x 72 registered sdram dimms advance a0 sa0 spd sda a1 sa1 a2 sa2 ras# cas# cke0 we# a0-a11 rras#: sdrams u0-u8 rcas#: sdrams u0-u8 rcke0: sdrams u0-u8 rwe#: sdrams u0-u8 ra0-ra11: sdrams u0-u8 rba0: sdrams u0-u8 rba1: sdrams u0-u8 rs0#, rs2# rdqmb0-rdqmb7 ba0 ba1 s0#, s2# dqmb0-dqmb7 pll clk v dd v ss sdrams u0-u8 sdrams u0-u8 dqm cs# u10 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 rdqmb7 dqm cs# u11 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 rdqmb6 dqm cs# u13 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 rdqmb5 dqm cs# u14 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 rdqmb4 dqm cs# u4 u5, u7 u6 u9 u8 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 rdqmb3 dqm cs# u3 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 rdqmb2 dqm cs# u2 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 rdqmb1 dqm cs# u1 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 rdqmb0 rs2# rs0# dqm cs# u12 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 rege v dd 10k r e g i s t e r wp pll sdram x 3 sdram x 3 sdram x 3 register x 2 ck0 12pf 12pf ck1-ck3 scl 47k u0-u8 = mt48lc8m8a2tg sdrams for 64mb u0-u8 = mt48lc16m8a2tg sdrams for 128mb note: 1. all resistor values are 10 ohms unless otherwise specified. functional block diagram mt9lsdt872 (64mb) and mt9lsdt1672 (128mb)
5 8, 16 meg x 72 pc133/pc100 registered sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm28_3.p65 ? rev. 4/00 ?1999, micron technology, inc. 8, 16 meg x 72 registered sdram dimms advance pin descriptions pin numbers symbol type description 27, 111, 115 we#, cas#, i nput command inputs: we#, ras#, and cas# (along with s0#, s2#) ras# define the command being entered. 42, 79, 125, 163 ck0-ck3 i nput clock: ck0 is distributed through an on-board pll to all devices. ck1-ck3 are terminated. 128 cke0 i nput clock enable: cke0 activates (high) and deactivates (low) the ck0 signal. deactivating the clock provides power-down and self refresh operation (all banks idle) or clock suspend operation (burst access in progress). cke0 is synchronous except after the device enters power-down and self refresh modes, where cke0 becomes asynchronous until after exiting the same mode. the input buffers, including ck0, are disabled during power-down and self refresh modes, providing low standby power. 30, 45 s0#, s2# i nput chip select: s0#, s2# enable (registered low) and disable (registered high) the command decoder. all commands are masked when s0#, s2# are registered high. s0#, s2# are considered part of the command code. 28-29, 46-47, dqmb0- input i nput/output mask: dqmb is an input mask signal for write 112-113, 130-131 dqmb7 accesses and an output enable signal for read accesses. input data is masked when dqmb is sampled high during a write cycle. the output buffers are placed in a high-z state (two-clock latency) when dqmb is sampled high during a read cycle. 122, 39 ba0, ba1 input bank address: ba0 and ba1 define to which bank the active, read, write or precharge command is being applied. 33, 117, 34, 118, 35, 119, a0-a11 input address inputs: a0-a11 are sampled during the active command 36, 120, 37, 121, 38, 123 (row-address a0-a11) and read/write command (column-address a0-a8/a9, with a10 defining auto precharge) to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine if both banks are to be precharged (a10 high). the address inputs also provide the op-code during a load mode register command. 8 1 wp input write protect: serial presence-detect hardware write protect. 8 3 scl input serial clock for presence-detect: scl is used to synchronize the presence-detect data transfer to and from the module. 165-167 sa0-sa2 input presence-detect address inputs: these pins are used to configure the presence-detect device. 147 rege input register enable. 2-5, 7-11, 13-17, 19-20, dq0-dq63 input/ data i/os: data bus. 55-58, 60, 65-67, 69-72, output 74-77, 86-89, 91-95, 97-101, 103-104, 139-142, 144, 149-151, 153-156, 158-161 21-22,0 52-53, 105-106, cb0-cb7 input/ check bits. 136-137 output
6 8, 16 meg x 72 pc133/pc100 registered sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm28_3.p65 ? rev. 4/00 ?1999, micron technology, inc. 8, 16 meg x 72 registered sdram dimms advance pin descriptions (continued) pin numbers symbol type description 8 2 sda input/ serial presence-detect data: sda is a bidirectional pin output used to transfer addresses and data into and data out of the presence-detect portion of the module. 6, 18, 26, 40-41, 49, 59, v dd supply power supply: +3.3v 0.3v. 73, 84, 90, 102, 110, 124, 133, 143, 157, 168 1, 12, 23, 32, 43, 54, 64, v ss supply ground. 68, 78, 85, 96, 107, 116, 127, 138, 148, 152, 162 63, 114, 126, 129, 132 rfu ? reserved for future use: these pins are not connected on this module but are assigned pins on other sdram versions. 31, 44, 48 dnu ? do not use: these pins are not connected on this module but are assigned pins on the compatible dram version.
7 8, 16 meg x 72 pc133/pc100 registered sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm28_3.p65 ? rev. 4/00 ?1999, micron technology, inc. 8, 16 meg x 72 registered sdram dimms advance serial presence-detect matrix byte description entry (version) mt9lsdt872 mt9lsdt1672 0 number of bytes used by micron 128 80 80 1 total number of spd memory bytes 256 08 08 2 memory type sdram 04 04 3 number of row addresses 12 0c 0c 4 number of column addresses 9 or 10 09 0a 5 number of banks 1 01 01 6 module data width 72 48 48 7 module data width (continued) 0 00 00 8 module voltage interface levels lvttl 01 01 9 sdram cycle time, t ck 7 (-13e) 70 70 (cas latency = 3) 7.5 (-133) 75 75 8 (-10e) 80 80 10 sdram access from clock, t ac 5.4 (-13e/-133) 54 54 (cas latency = 3) 6 (-10e) 60 60 11 module configuration type ecc 02 02 12 refresh rate/type 15.6s/self 80 80 13 sdram width (primary sdram) 8 08 08 14 error-checking sdram data width 8 08 08 15 min. clock delay from back-to-back 1 01 01 random column addresses, t ccd 16 burst lengths supported 1, 2, 4, 8, page 8f 8f 17 number of banks on sdram device 4 04 04 18 cas latencies supported 2, 3 06 06 19 cs latency 0 01 01 20 we latency 0 01 01 21 sdram module attributes -13e/-133 1f 1f -10e 16 16 22 sdram device attributes: general 0e 0e 0e 23 sdram cycle time, t ck 7.5 (-13e) 75 75 (cas latency = 2) 10 (-133/-10e) a0 a0 24 sdram access from clk, t ac 5.4 (-13e) 54 54 (cas latency = 2) 6 (-10e) 60 60 25 sdram cycle time, t ck ? 00 00 (cas latency = 1) 26 sdram access from clk, t ac ? 00 00 (cas latency = 1) 27 minimum row precharge time, t rp 15 (-13e) 0f 0f 20 (-133/-10e) 14 14 14 (-13e) 0e 0e 28 minimum row active to row active, 14 (-13e) 0e 0e t rrd 15 (-133) 0f 0f 20 (-10e) 14 14 29 minimum ras# to cas# delay, t rcd 15 (-13e) 0f 0f 20 (-133/-10e) 14 14 37 (-13e) 25 25 note: 1. ? 1 ? / ? 0 ? : serial data, ? driven to high ? / ? driven to low. ?
8 8, 16 meg x 72 pc133/pc100 registered sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm28_3.p65 ? rev. 4/00 ?1999, micron technology, inc. 8, 16 meg x 72 registered sdram dimms advance serial presence-detect matrix (continued) byte d escription entry (version) mt9lsdt872 mt9lsdt1672 30 minimum ras# pulse width, 45 (-13e) 2d 2d ( t ras module = t rc - t rp) 44 (-133) 2c 2c 50 (-10e) 32 32 31 module bank density 64mb/128mb 10 20 32 command and address setup time, 1.5 (-13e/-133) 15 15 t as, t cms 2 (-10e) 20 20 33 command and address hold time, 0.8 (--13e/133) 08 08 t ah, t cmh 1 (-10e) 10 10 34 data signal input setup time, t ds 1.5 (-13e/-133) 15 15 2 (-10e) 20 20 35 data signal input hold time, t dh 0.8 (-13e/-133) 08 08 1 (-10e) 10 10 36-61 res erved 00 00 62 spd revision rev. 1.2 12 12 63 checksum for bytes 0-62 -13e 88 99 -133 c5 ce -10e 0d 16 64 manufacturer?s jedec id code micron 2c 2c 65-71 manufacturer?s jedec id code (cont.) ff ff 72 manufacturing location 01 01 02 02 03 03 04 04 05 05 06 06 07 07 08 08 09 09 73-90 module part number (ascii) xx xx 91 pcb identification code 1 01 01 20202 30303 40404 50505 60606 70707 80808 90909 92 identification code (cont.) 0 00 00 93 year of manufacture in bcd xx xx 94 week of manufacture in bcd xx xx 95-98 module serial number xx xx 99-125 manufacturer-specific data (rsvd) ? ? 126 system frequency 100/133 mhz 64 64 127 sdram component and clock detail 8f 8f note: 1. ?1?/?0?: serial data, ?driven to high?/?driven to low.? 2. x = variable data.
9 8, 16 meg x 72 pc133/pc100 registered sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm28_3.p65 ? rev. 4/00 ?1999, micron technology, inc. 8, 16 meg x 72 registered sdram dimms advance note: 1. cke is high for all commands shown except self refresh. 2. a0-a11 define the op-code written to the mode register. 3. a0-a11 provide row address, and ba0, ba1 determine which bank is made active. 4. a0-a8/a9 provide column address; a10 high enables the auto precharge feature (nonpersistent), while a10 low disables the auto precharge feature; ba0, ba1 determine which bank is being read from or written to. 5. a10 low: ba0, ba1 determine which bank is being precharged. a10 high: both banks are precharged and ba0, ba1 are ? don ? t care. ? 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are ? don ? t care ? except for cke. 8. activates or deactivates the dqs during writes (zero-clock delay) and reads (two-clock delay). truth table 1 ? commands and dqmb operation (note: 1) name (function) cs# ras# cas# we# dqmb addr dqs notes command inhibit (nop) h x x x x x x no operation (nop) l h h h x x x active (select bank and activate row) l l h h x bank/row x 3 read (select bank and column, and start read burst) l h l h l/h 8 bank/col x 4 write (select bank and column, and start write burst) l h l l l/h 8 bank/col valid 4 burst terminate l h h l x x active precharge (deactivate row in bank or banks) l l h l x code x 5 auto refresh or l l l h x x x 6, 7 self refresh (enter self refresh mode) load mode register l l l l x op- code x 2 write enable/output enable ???? l ? active 8 write inhibit/output high-z ???? h ? high-z 8 commands truth table 1 provides a quick reference of available commands. this is followed by a written description of each command. for a more detailed description of commands and operations refer to the 64mb, 128mb x4, x8, x16 sdram datasheets.
10 8, 16 meg x 72 pc133/pc100 registered sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm28_3.p65 ? rev. 4/00 ?1999, micron technology, inc. 8, 16 meg x 72 registered sdram dimms advance note: 1. for full-page accesses: y = 1,024 (128mb), y = 512 (64mb) 2. for a burst length of two, a1-a9/a8 select the block of two burst; a0 selects the starting column within the block. 3. for a burst length of four, a2-a9/a8 select the block of four burst; a0-a1 select the starting column within the block. 4. for a burst length of eight, a3-a9/a8 select the block of eight burst; a0-a2 select the starting column within the block. 5. for a full-page burst, the full row is selected and a0-a9/a8 select the starting column. 6. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. for a burst length of one, a0-a9/a8 select the unique column to be accessed, and mode register bit m3 is ignored. table 1 burst definition burst starting column order of accesses within a burst length address type = sequential type = interleaved a0 2 0 0-1 0-1 1 1-0 1-0 a1 a0 0 0 0-1-2-3 0-1-2-3 4 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full n = a0-9/8 cn, cn+1, cn+2 page (location 0-y) cn+3, cn+4... not supported (y) ? cn-1, cn ? m2 0 0 0 0 1 1 1 1 m1 0 0 1 1 0 0 1 1 m0 0 1 0 1 0 1 0 1 m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 - 0 - defined - 0 1 burst type sequential interleaved cas latency reserved 2 3 reserved reserved reserved reserved m6 0 0 0 1 1 1 1 m4 0 0 1 0 1 0 1 m5 0 1 1 0 0 1 1 burst length burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m3 m6-m0 m8 m7 op mode a10 a11 10 11 reserved* 12 unused wb 0 1 write burst mode programmed burst length single location access m9 *should program m11, m10 = ? 0, 0 ? to ensure compatibility with future devices. figure 4 mode register definition
11 8, 16 meg x 72 pc133/pc100 registered sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm28_3.p65 ? rev. 4/00 ?1999, micron technology, inc. 8, 16 meg x 72 registered sdram dimms advance absolute maximum ratings* voltage on v dd supply relative to v ss . -1v to +4.6v voltage on inputs, nc or i/o pins relative to v ss ...................................... -1v to +4.6v operating temperature, t a (ambient) ... 0c to +70c storage temperature (plastic) .......... -55c to +125c power dissipation ................................................ 18w *stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied. exposure to abso- lute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics and operating conditions (notes: 1, 2) (v dd = +3.3v 0.3v) parameter/condition symbol min max units notes supply voltage v dd 3 3.6 v input high voltage: logic 1; all inputs v ih 2v dd + 0.3 v 3 input low voltage: logic 0; all inputs v il -0.5 0.8 v 3 input leakage current: i i 1 -5 5 a 4 any input 0v v in v dd (all other pins not under test = 0v) output leakage current: i oz -5 5 a dqs are disabled; 0v v out v dd output levels: v oh 2.4 ? v output high voltage (i out = -4ma) output low voltage (i out = 4ma) v ol ? 0.4 v note: 1. all voltages referenced to v ss . 2. an initial pause of 100s is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 3. v ih overshoot: v ih (max) = v dd + 2v for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. v il undershoot: v il (min) = -2v for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. 4. input leakage values based on register electrical characteristics, v dd = 3.6v.
12 8, 16 meg x 72 pc133/pc100 registered sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm28_3.p65 ? rev. 4/00 ?1999, micron technology, inc. 8, 16 meg x 72 registered sdram dimms advance i dd specifications and conditions (notes: 1-4) (v dd = +3.3v 0.3v) parameter/condition symbol size -13e -133 -10e units notes operating current: active mode; i dd 1 64mb 1,125 1,035 855 ma 5, 6, burst = 2; read or write; t rc = t rc (min); cas latency = 3 128mb 1,440 1,350 1,260 7, 8 standby current: power-down mode; i dd 2 64mb 18 18 18 ma 8 cke = low; all banks idle 128mb 18 18 18 standby current: active mode; s0#, s2# = high; i dd 3 64mb 405 405 315 ma 5, 7, cke = high;all banks active after t rcd met; 8, 9 no accesses in progress 128mb 450 450 360 operating current: burst mode; continuous burst; i dd 4 64mb 1,350 1,260 1,080 ma 5, 6, read or write; all banks active; cas latency = 3 128mb 1,485 1,350 1,260 7, 8 auto refresh current: cke = high; t rc = t rc (min); i dd 5 64mb 2,070 1,890 1,710 ma 5, 6, 7, s0#, s2# = high cl = 3 128mb 2,970 2,790 2,430 8, 9 t rc = 15.625s; i dd 6 64mb 27 27 27 ma cl = 3 128mb 27 27 27 self refresh current: cke 0.2v i dd 7 64mb 9 9 9 ma 10 128mb 18 18 18 max note: 1. all voltages referenced to v ss . 2. an initial pause of 100s is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 3. ac timing and i dd test have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point. if the input transition time is longer than 1ns, then the timing is referenced at v il (max) and v il (min) and no longer at the 1.5v crossover point. 4. i dd specifications are tested after the device is properly initialized. 5. i dd is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 6. the i dd current will decrease as the cas latency is reduced. this is due to the fact that the maximum cycle rate is slower as the cas latency is reduced. 7. address transitions average one transition every two clocks. 8. t ck = 7ns for -13e; t ck = 7.5ns for -133; t ck = 10ns for -10e. 9. other input signals are allowed to transition no more than once every two clocks and are otherwise at valid v ih or v il levels. 10. enables on-chip refresh and address counters.
13 8, 16 meg x 72 pc133/pc100 registered sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm28_3.p65 ? rev. 4/00 ?1999, micron technology, inc. 8, 16 meg x 72 registered sdram dimms advance sdram component* ac electrical characteristics (notes: 2, 3, 4, 5, 6, 7) ac characteristics -13e -133 -10e parameter symbol min max min max min max units notes access time from clk cl = 3 t ac 5.4 5.4 6 ns 8 (positive edge) cl = 2 t ac 5.4 6 6 ns address hold time t ah 0.8 0.8 1 ns address setup time t as 1.5 1.5 2 ns clk high level width t ch 2.5 2.5 3 ns clk low level width t cl 2.5 2.5 3 ns clock cycle time cl = 3 t ck 7 7.5 8 ns 9 cl = 2 t ck 7.5 10 10 ns 9 cke hold time t ckh 0.8 0.8 1 ns cke setup time t cks 1.5 1.5 2 ns cs#, ras#, cas#, we#, dqm hold time t cmh 0.8 0.8 1 ns cs#, ras#, cas#, we#, dqm setup time t cms 1.5 1.5 2 ns data-in hold time t dh 0.8 0.8 1 ns data-in setup time t ds 1.5 1.5 2 ns data-out high-impedance time cl = 3 t hz 5.4 5.4 6 ns 10 cl = 2 t hz 5.4 6 7 ns 10 data-out low-impedance time t lz111ns data-out hold time (load) t oh 2.7 2.7 3 ns data-out hold time (no load) t oh n 1.8 1.8 1.8 ns 11 active to precharge command t ras 37 120,000 44 120,000 50 120,000 ns active to active command period t rc 60 66 70 ns active to read or write delay t rcd152020ns refresh period (4,096 cycles) t ref 64 64 64 ms auto refresh period `t rfc 66 66 70 ns precharge command period t rp 15 20 20 ns active bank a to active bank b command t rrd141520ns transition time t t 0.3 1.2 0.3 1.2 0.3 1.2 ns 12 write recovery time t wr 1 clk + 1 clk + 1 clk + ? 13 7ns 7.5ns 7ns 14 15 15 ns 14 exit self refresh to active command t xsr 67 75 80 ns capacitance parameter symbol max units input capacitance: a0-a11, ba0, ba1, ras#, cas#, we# c i 1 8pf input capacitance: s0#, s2#, cke0, dqmb0#-dqmb7# c i 2 8pf input capacitance: ck0 c i 3 6pf input capacitance: rege c i 4 5pf input capacitance: scl, sa0-sa2, wp c i 5 12 p f input/output capacitance: dq0-dq63, cb0-cb7, sda c i o 8pf *specifications for the sdram components used on the module. note: this parameter is sampled. v dd = +3.3v; f = 1 mhz.
14 8, 16 meg x 72 pc133/pc100 registered sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm28_3.p65 ? rev. 4/00 ?1999, micron technology, inc. 8, 16 meg x 72 registered sdram dimms advance note: 1. this parameter is sampled. v dd = +3.3v; f = 1 mhz. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0 c t a +70 c) is ensured. 6. an initial pause of 100s is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 7. ac characteristics assume t t = 1ns. 8. in addition to meeting the transition rate specification, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 9. outputs measured at 1.5v with equivalent load: 10. t hz defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 11. ac timing and i dd test have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point. if the input transition time is longer than 1ns, then the timing is referenced at v il (max) and v il (min) and no longer at the 1.5v crossover point. 24. there will be an added one-clock latency at the system level due to the register requiring an added clock cycle. 26. auto precharge mode only. the precharge timing budget ( t rp) begins 7.5ns/7ns after the first clock delay, after the last write is executed. 27. precharge mode only. 28. the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (read, write, including t wr, and precharge commands). cke may be used to reduce the data rate. 30. t ac for -133 at cl = 3 with no load is 4.6ns and is guaranteed by design. 32. parameter guaranteed by design. q 50pf
15 8, 16 meg x 72 pc133/pc100 registered sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm28_3.p65 ? rev. 4/00 ?1999, micron technology, inc. 8, 16 meg x 72 registered sdram dimms advance ac functional characteristics (notes: 1-7) parameter symbol -133 -13e/-10e units notes read/write command to read/write command t ccd 1 1 t ck 8 cke to clock disable or power-down entry mode t cked 1 1 t ck 9 cke to clock enable or power-down exit setup mode t ped 1 1 t ck 9 dqm to input data delay t dqd 0 0 t ck 8 dqm to data mask during writes t dqm 0 0 t ck 8 dqm to data high-impedance during reads t dqz 2 2 t ck 8 write command to input data delay t dwd 0 0 t ck 8 data-in to active command t dal 5 4 t ck 10, 11 data-in to precharge command t dpl 2 2 t ck 11, 12 last data-in to burst stop command t bdl 1 1 t ck 8 last data-in to new read/write command t cdl 1 1 t ck 8 last data-in to precharge command t rdl 2 2 t ck 11, 12 load mode register command to active or refresh command t mrd 2 2 t ck 13 data-out to high-impedance from precharge command cl = 3 t roh 3 3 t ck 8 cl = 2 t roh 2 2 t ck 8 note: 1. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0 c t a +70 c) is ensured. 2. an initial pause of 100s is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 3. ac characteristics assume t t = 1ns. 4. in addition to meeting the transition rate specification, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 5. outputs measured at 1.5v with equivalent load: 6. ac timing and i dd test have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point. if the input transition time is longer than 1ns, then the timing is referenced at v il (max) and v il (min) and no longer at the 1.5v crossover point. 7. there will be an added one-clock latency at the system level due to the register requiring an added clock cycle. 8. required clocks are specified by jedec functionality and are not dependent on any timing parameter. 9. timing actually specified by t cks; clock(s) specified as a reference only at minimum cycle rate. 10. timing actually specified by t wr plus t rp; clock(s) specified as a reference only at minimum cycle rate. 11. based on t ck = 143 mhz for -13e, t ck = 133 mhz for -133, 100 mhz for -10e. 12. timing actually specified by t wr. 13. jedec and pc100 specify three clocks. q 50pf
16 8, 16 meg x 72 pc133/pc100 registered sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm28_3.p65 ? rev. 4/00 ?1999, micron technology, inc. 8, 16 meg x 72 registered sdram dimms advance serial presence-detect eeprom dc operating conditions (note: 1) (v dd = +3.3v 0.3v) parameter/condition symbol min max units supply voltage v dd 3 3.6 v input high voltage: logic 1; all inputs v ih v dd x 0.7 v dd + 0.5 v input low voltage: logic 0; all inputs v il -1 v dd x 0.3 v output low voltage: i out = 3ma v ol ? 0.4 v input leakage current: v in = gnd to v dd i li ? 10 a output leakage current: v out = gnd to v dd i lo ? 10 a standby current: i sb ? 30 a scl = sda = v dd - 0.3v; all other inputs = gnd or 3.3v +10% power supply current: i dd ? 2ma scl clock frequency = 100 khz serial presence-detect eeprom ac operating conditions (note: 1) (v dd = +3.3v 0.3v) parameter/condition symbol min max units notes scl low to sda data-out valid t a a 0.3 3.5 s time the bus must be free before a new transition can start t buf 4.7 s data-out hold time t d h 300 ns sda and scl fall time t f 300 ns data-in hold time t hd:dat 0 s start condition hold time t hd:sta 4 s clock high period t high 4 s noise suppression time constant at scl, sda inputs t i 100 ns clock low period t low 4.7 s sda and scl rise time t r1s scl clock frequency t scl 100 khz data-in setup time t su:dat 250 ns start condition setup time t su:sta 4.7 s stop condition setup time t su:sto 4.7 s write cycle time t wrc 10 ms 2 note: 1. all voltages referenced to v ss . 2. the spd eeprom write cycle time ( t wrc) is the time from a valid stop condition of a write sequence to the end of the eeprom internal erase/program cycle. during the write cycle, the eeprom bus interface circuit is disabled, sda remains high due to pull-up resistor, and the eeprom does not respond to its slave address.
17 8, 16 meg x 72 pc133/pc100 registered sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm28_3.p65 ? rev. 4/00 ?1999, micron technology, inc. 8, 16 meg x 72 registered sdram dimms advance serial presence-detect eeprom timing parameters symbol min max units t aa 0.3 3.5 s t buf 4.7 s t dh 300 ns t f 300 ns t hd:dat 0 s t hd:sta 4 s spd eeprom scl sda in sda out t low t su:sta t hd:sta t f t high t r t buf t dh t aa t su:sto t su:dat t hd:dat undefined symbol min max units t high 4 s t low 4.7 s t r1s t su:dat 250 ns t su:sta 4.7 s t su:sto 4.7 s
18 8, 16 meg x 72 pc133/pc100 registered sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. zm28_3.p65 ? rev. 4/00 ?1999, micron technology, inc. 8, 16 meg x 72 registered sdram dimms advance 168-pin dimm (64mb/128mb) pin 1 .700 (17.78) .118 (3.00) (2x) .118 (3.00) .250 (6.35) 4.550 (115.57) .050 (1.27) .118 (3.00) .040 (1.02) .079 (2.00) r (2x) .039 (1.00) r(2x) pin 84 front view .157 (4.00) max .054 (1.37) .046 (1.17) .128 (3.25) .118 (3.00) (2x) back view pin 168 pin 85 2.625 (66.68) 1.661 (42.18) 1.505 (38.23) 1.495 (37.97) 5.256 (133.50) 5.244 (133.20) note: 1. all dimensions in inches (millimeters) max or typical where noted. min 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micronsemi.com, internet: http://www.micronsemi.com, customer comment line: 800-932-4992 micron is a registered trademark of micron technology, inc.

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